Shape the future of silicon design by leading the physical implementation of next-generation in-memory computing systems-on-chip. In this role, you'll own the full ASIC physical design flow, from synthesis through to GDS signoff, ensuring high-performance, power-efficient designs that meet stringent timing and area targets.
What You'll Do
- Lead synthesis, floorplanning, placement, routing, extraction, and timing closure for complex multi-core SoCs.
- Generate timing constraints and perform detailed timing analysis and optimization across multiple corners.
- Implement clock tree synthesis and develop custom clocking strategies to meet aggressive skew and jitter requirements.
- Integrate diverse IP blocks including memory subsystems, embedded processors, DDR interfaces, analog components, and high-speed interconnects.
- Apply advanced physical verification techniques using industry-standard tools to ensure manufacturability and reliability.
- Write and maintain automation scripts in Python, Tcl, and Bash to streamline design flows and improve team efficiency.
- Collaborate with architecture, RTL, and verification teams to resolve cross-functional challenges and ensure a robust design from concept to tapeout.
What We're Looking For
- Minimum of 10 years of hands-on experience in ASIC physical design, covering the complete RTL-to-GDS flow.
- Proven mastery of EDA tools including Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, Fusion Compiler, and Calibre.
- Strong background in timing analysis, constraint management, and optimization techniques.
- Experience with clock tree synthesis and low-jitter clock distribution strategies.
- Track record of successful IP integration across digital, analog, and mixed-signal domains.
- Proficiency in scripting languages such as Python and Tcl for flow automation and data analysis.
- Excellent problem-solving skills with the ability to debug and resolve complex physical design issues.
- Fluency in English, both written and spoken, with strong interpersonal and collaboration abilities.
Preferred Background
- Experience in top-level floorplanning and system-level integration.
- Familiarity with chip-package-board co-simulation and packaging effects.
- Direct engagement with EDA vendors to troubleshoot and resolve tool-related issues.
- Understanding of semiconductor device physics and multi-domain design challenges.
Work Environment
This role offers flexible working arrangements—choose to work from one of our European locations or remotely from any European country. Onsite hubs are located in Leuven (Belgium), Amsterdam and Eindhoven (Netherlands), Florence and Milan (Italy), and Bristol (UK). Relocation support is available for select locations. We prioritize candidates based in Belgium or Italy.
Compensation & Benefits
- Competitive salary with a comprehensive pension plan.
- Extensive health and employee insurance coverage.
- Opportunity to receive company shares as part of your compensation.
- Inclusive culture that values creativity, innovation, and individual ownership.
- Commitment to diversity, equity, and inclusion across all levels of the organization.
- A supportive environment where every team member is empowered and recognized.
