Responsibilities
- Own chip floor planning, partition creation, clock tree and delivery of top level partitions
- Resolve physical design issues related to chip integration and assembly
- Manage all cross functional interactions related to top level floorplanning, I/O and bump planning with package team
- Develop and improve floorplan methodologies using both industry and internal tools
- Perform technical evaluations of IPs, providing recommendations and assessments to meet design specification
Requirements
- Bachelors and 8+ years of experience in top level floorplanning with a focus on die size estimate, partitioning, clocking and pin assignment, or Master's degree in Electrical Engineering and 6+ years of experience in top level floorplanning with a focus on die size estimate, partitioning, clocking and pin assignment
- Experience working on various technologies (Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, chiplet etc)
- Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes and tape out experience
- Proven track record with bump planning, RDL routes and multi voltage domain designs
- Experience with hierarchical design planning, power grid design, structured clocks, top level pipeline placement, custom routes and bump planning
- Experience in collaborating with design, package and methodology teams during development phase
- Experience in scripting languages like Python, Tcl, or Perl
Benefits
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- company paid holidays
- paid sick leave and vacation time
- Paid Family Leave and other leaves of absence
Additional Information
- Must work in person at our San Jose site and no remote work allowed
- If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
