As a Verification Engineer, you will play a key role in validating custom AI accelerator designs, ensuring RTL implementations fully align with specifications and performance targets. You'll develop and execute comprehensive verification strategies, building robust, automated test environments that scale with design complexity.
Key Responsibilities
- Develop and maintain verification plans to validate RTL against functional and performance requirements.
- Construct and optimize testbenches using SystemVerilog and UVM or CocoTB methodologies.
- Automate workflows using Python, Tcl, or shell scripting to improve efficiency and coverage.
- Collaborate with RTL designers, architects, and software teams to resolve issues and refine verification approaches.
- Contribute to the evolution of verification practices across the team and influence technical direction.
Qualifications
A degree in electrical engineering, computer science, or a related field is required, along with at least three years of hands-on experience in ASIC or FPGA verification. Proficiency in SystemVerilog and scripting languages such as Python or Tcl is essential. You should also have a proven ability to work across technical domains and communicate effectively in English.
Experience with emulation platforms, commercial simulation tools, or formal verification methods is advantageous. Familiarity with UVM or CocoTB frameworks will support your success in this role.
Work Environment
This role supports flexible working across Europe, with options to work remotely or from local offices in Belgium, the Netherlands, Switzerland, Italy, or the UK. The team values ownership, innovation, and collaboration, operating in a culture that promotes inclusion, creativity, and technical excellence.
Compensation includes a competitive package, pension benefits, comprehensive insurance, and the opportunity to receive company shares. The organization is committed to equal opportunity and welcomes applicants from all backgrounds.
