Responsibilities
- Develop and deploy scan chains, ATPG, memory BIST, JTAG/IJTAG, and fault simulation workflows.
- Work closely with RTL, verification, and physical design groups to ensure seamless DFT integration.
- Assist in silicon bring-up and debugging to improve test coverage and manufacturing yield.
- Drive enhancements in DFT methodologies and promote knowledge sharing within the team.
Benefits
- Competitive salary and bonus structure
- Retirement savings plan
- Comprehensive health and welfare insurance coverage
- Eligibility to receive equity in the company
Compensation
Attractive compensation package
Work Arrangement
Remote (Country)
Team
Collaborative environment valuing innovation, ownership, and inclusivity
Other
- Preference given to candidates open to being based in Belgium or Italy.
- Opportunity to relocate to Florence or Milan in Italy, or Amsterdam or Eindhoven in the Netherlands.
- Work culture that encourages creative thinking and ongoing technical innovation.
- Team members operate with autonomy, supported by a sense of shared responsibility.
- Commitment to equal opportunity, diversity, and fostering an inclusive workplace.
