As the Principal Power Architect, you will define and own the comprehensive power strategy for advanced SSD and system-on-chip (SoC) platforms. Your work will shape how these systems manage energy across active, idle, and low-power states, ensuring optimal performance per watt while maintaining reliability and responsiveness across client, enterprise, and hyperscale workloads.
Key Responsibilities
- Establish the full-stack power architecture for future SSD SoCs, including policies for dynamic state transitions and power-state sequencing.
- Design and implement dynamic power management (DPM) frameworks that span firmware, SoC logic, and NAND subsystems.
- Lead cross-architecture analysis to balance power, performance, and thermal behavior, setting measurable targets for efficiency across usage scenarios.
- Collaborate with SoC design teams to define power domain structures, voltage and clocking strategies, and fine-grained power gating techniques.
- Partner with firmware architects to develop intelligent power governors that adapt to workload patterns and system conditions.
- Build and refine predictive power models using real-world telemetry, guiding pre-silicon design and post-silicon validation.
- Develop rigorous methodologies to measure, simulate, and correlate power behavior across development stages.
- Work closely with NAND engineering to optimize power consumption during flash operations, particularly under mixed and sustained workloads.
- Define thermal design parameters and performance margins in coordination with packaging and mechanical engineering teams.
- Evaluate competitive offerings to ensure continued leadership in energy efficiency and thermal scalability.
Qualifications
Candidates should hold an M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or a related discipline, or demonstrate equivalent industry experience. A minimum of 10 years in SoC or storage system architecture with a focus on power optimization is required.
Essential expertise includes deep knowledge of low-power SoC design principles such as dynamic voltage and frequency scaling (DVFS), clock gating, power islands, and retention strategies. Experience with firmware-level power control loops in SSDs or similar embedded systems is critical. Proficiency in both pre- and post-silicon power modeling and measurement is expected, along with familiarity with thermal management, voltage regulation, and workload characterization.
Preferred qualifications include exposure to high-speed interfaces such as PCIe/NVMe or CXL, experience with chiplet-based power domains, and background in machine learning–driven power prediction or adaptive workload management. Familiarity with tools like PowerArtist, PrimePower, or SystemC is advantageous. Demonstrated leadership in complex, cross-functional technical initiatives is highly valued.
Work Environment
This role operates in a hybrid work model, with primary locations in Rancho Cordova, California; Longmont, Colorado; and Vancouver, British Columbia. The culture emphasizes inclusion, collaboration, and innovation, supporting employees to contribute authentically in a results-driven, team-oriented environment.
