New Delhi, India Remote (City)

Altera is hiring a Principal Logic Design Engineer

Responsibilities

  • Engage in design development activities across all stages of IP creation.
  • Create logic designs, write register transfer level (RTL) code, and perform simulations for IP components.
  • Design and implement RTL for IP used to build cell libraries, functional units, IP blocks, and subsystems intended for full chip integration.
  • Apply diverse methodologies, tools, and techniques to write and optimize RTL, ensuring designs meet quality benchmarks for IP release.
  • Support the creation of design examples, simulation test cases, and participate in IP integration and release workflows.
  • Participate in hardware bring-up of IP design examples, conduct hardware validation, and debug failures.

Work Arrangement

Remote (City/Region)

Shift

Shift 1 (India)

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Required Skills
C/C++PerlPython
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About company
Altera
Altera, a leader in programmable solutions from cloud to edge, delivers cutting-edge FPGA, CPLD, and IP technologies. The company drives innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure.
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Job Details
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Posted 5 months ago