Altera is hiring a Principal Logic Design Engineer to lead the development and optimization of mixed-signal and high-speed IPs for our full-chip designs. You will be instrumental in driving IP from logic design through to hardware verification.
What You'll Do
- Participate in design development tasks throughout the IP development flow.
- Develop logic design, register transfer level (RTL) coding, and simulation for IPs.
- Apply various strategies, tools, and methods to write RTL and optimize logic to meet IP release requirements.
- Contribute to design example creation, simulation example creation, IP integration, and the release process.
- Bring up IP design examples on hardware, perform hardware verification, and debug failures.
What We're Looking For
- 15+ years of experience with a bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience in System Verilog, VCS/Synopsys simulators, Lint, and Synthesis.
- Experience in programming with C/C++/Perl/Python/TCL/Unix Shell script.
- Ability to work with different teams, coupled with strong communication and problem-solving skills.
Nice to Have
- Experience in FPGA design and programming.
- Experience in RTL validation.
Technical Stack
- System Verilog, VCS/Synopsys simulators, Lint, Synthesis
- C/C++, Perl, Python, TCL, Unix Shell script
- FPGA
Work Mode
This position operates in a local-country work mode and is based in New Delhi, India or Bengaluru, Karnataka, India.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
