Micron is looking for a Principal Engineer to focus on high-speed PHY design in advanced technology nodes. In this role, you will own analog sub-blocks, drive specifications and implementation, and participate in silicon bring-up and characterization as part of a team pushing the boundaries of memory interfaces.
What You'll Do
- Be part of a highly skilled team designing high-speed PHYs for technology nodes at 12nm and below.
- Take ownership of analog sub-blocks inside the PHY, driving specification and implementation, including transistor and block-level design, simulation, reliability, and mixed-mode simulations.
- Drive the layout of complex blocks through mask designers, conforming to complex process rules and DFM.
- Participate in design reviews internally and with customers to explain design choices and robustness.
- Help create IP EDA views: Behavioral/Verilog-A, timing views, abstract, etc.
- Participate in silicon bring-up, characterization, and perform correlations against models and simulations.
- Mentor and supervise junior engineers.
What We're Looking For
- 5+ years of circuit design experience in analog/mixed-signal CMOS circuits in deep sub-micron technologies (2 – 28 nm) for High-speed Memory interfaces (DDR3/4/5, LPDDR5/6, GDDR5/6/7) or SerDes Interfaces (PCIe, MIPI, HDMI, USB, SATA, etc.).
- Prior experience taking full ownership of at least one sub-block like PLL, DLL, CDR, high-speed receiver with equalization, transmitter front end, or high-speed data path.
- Deep understanding of analog and mixed-signal circuits for high-speed links.
- Experience with Serdes/Parallel Interface and TX RX Equalization (FFE/CTLE/DFE).
- Experience with various CDR and Clocking architectures.
- Hands-on experience in finfet 10nm and below.
- Able to create block-level specification based on link budget and system-level modeling using VerilogA/Python.
- Ability to work with Packaging/Board teams and knowledge of ESD.
- Experience in lab testing and working with validation teams to analyze data.
- Experience with high-speed I/O cell designs (DDR, LVDS, HSTL, CML) and Power Delivery circuits (Bandgap, LDO, Bias circuits).
- Strong fundamental knowledge for AMS design, Advanced CMOS and FinFet technologies.
- Understanding of Mismatch analysis & Monte-Carlo methodology/sims, transistor-level Circuit level noise analysis, device physics & deep-sub micron issues.
- Experience supervising complex and/or sensitive analog layout and defining IP floorplans.
- Proficiency with industry-standard tools such as Cadence ADE, Spectre, AMS verification, EM/IR flows, MATLAB, Calibre, etc.
- Working knowledge of Mixed mode simulation, Signal Integrity and ESD desired.
- M.S./M.Tech, BS/BE (Electronics).
Technical Stack
- Cadence ADE, Spectre, AMS verification, EM/IR flows
- MATLAB, Calibre
- VerilogA, Python
Team & Environment
You will work with people across multiple sites, including overseas.
Benefits & Compensation
- This is an equal opportunity position with an excellent pay package.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.
