Responsibilities
- To be part of a highly skilled and challenging high speed PHY design team working on the latest technology nodes (12nm and below).
- Take ownership of analog sub-blocks inside the PHY and drive the specification and implementation. It includes transistor and block level design, simulation, reliability and mixed mode simulations etc.
- Drive layout of complex blocks through mask designers. Conform to complex process rules as well as DFM.
- Participate in design reviews both internally and potentially with customers to explain design choices and robustness. Work with people across multiple sites including overseas.
- Help with creating IP EDA views: Behavioral/Verilog-A, timing views, abstract etc.
- Participate in silicon bring up, characterization, & perform correlations against models & simulations.
- Mentor and supervise junior engineers.
- Equal opportunity position with excellent pay package!
Requirements
- Circuit design experience in analog/mixed signal CMOS circuits in deep sub-micron technologies (2 – 28 nm) in High speed Memory interfaces (DDR3/4/5, LPDDR5/6, GDDR5/6/7) or SerDes Interfaces (PCIe, MIPI, HDMI, USB, SATA etc).
- Prior experience in taking full ownership of at least one of the sub-blocks like PLL, DLL, CDR, high speed receiver with equalization, transmitter front end and high speed data path.
- Candidate should have deep understanding of analog and mixed signal circuit with experience in high speed link.
- Candidate must have experience in Serdes/Parallel Interface.
- Experience with TX RX Equalization (FFE/CTLE/DFE) is must
- Experience with various CDR and Clocking architecture.
- Candidate should have experience in finfet 10nm and below.
- Able to create block level specification based on link budget.
- Able to create system level modeling using VerilogA/Python.
- Should be able to work with Packaging/Board team.
- Should have knowledge of ESD.
- Experience in lab testing and work with validation team to analysis data.
- High speed I/O cell designs such as DDR, LVDS, HSTL, CML.
- Power Delivery circuits such as Bandgap, LDO, Bias circuits.
- Strong fundamental knowledge for AMS design, Advanced CMOS and FinFet technologies.
- Understanding of Mismatch analysis & Monte-Carlo methodology/sims, transistor level Circuit level noise analysis. Understanding of device physics & deep-sub micron issues.
- Supervision of complex and/or sensitive analog layout and defining IP floorplan
- Experience with industry standard tools such as Cadence ADE, Spectre, AMS verification, EM/IR flows, MATLAB, Calibre etc.
Nice to Have
- Working knowledge of Mixed mode simulation, Signal Integrity and ESD desired.
Benefits
- Excellent pay package
- Equal opportunity employer
- Commitment to integrity, sustainability, and giving back to communities
Additional Information
- All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.
- Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
- Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
- Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
- Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website.
