We are seeking an experienced Physical Design Engineer to play a central role in the development of next-generation artificial intelligence and PCIe switch products. This position takes full responsibility for the physical design of complex ASICs, guiding them from RTL through to silicon tapeout.
Key Responsibilities
- Lead chip floorplanning, including partition definition, clock tree strategy, and delivery of top-level physical blocks
- Identify and resolve integration challenges related to chip assembly and physical constraints
- Coordinate with packaging teams on I/O layout, bump planning, and RDL routing
- Refine and optimize floorplanning methodologies using both commercial and internal tools
- Evaluate IP blocks for physical compatibility and provide technical feedback to ensure alignment with design goals
Qualifications
Candidates must be able to work on site in San Jose. Remote arrangements are not supported for this role.
Preferred candidates will have a Bachelor’s degree with 12+ years or a Master’s degree with 10+ years of hands-on experience in top-level floorplanning, including expertise in die sizing, partitioning, clock distribution, and pin placement. Experience with high-speed interfaces such as SerDes, HBM, DDR, and chiplet-based architectures is highly valued.
Additional preferred qualifications include hierarchical planning, power grid implementation, structured clocking, custom routing, and multi-voltage domain designs. Familiarity with DRC, LVS, and EMIR signoff for advanced process nodes is essential. Proficiency in scripting with Python, Tcl, or Perl is required to automate and enhance design flows.
Technical Environment
The role utilizes industry-standard physical design tools alongside proprietary internal platforms. Scripting and automation in Python, Tcl, and Perl are integral to improving efficiency and accuracy.
Work Environment
This is an on-site role based in San Jose, requiring in-person collaboration throughout the design cycle.
